A non-volatile memory retains the contents of the information stored in a memory cell even when the power is turned off. Many System-on-Chip (SoC) design teams find themselves confronting a seeming conundrum: How to design non-volatile memory (NVM) into a SoC project. To achieve a single chip solution, the design team typically has little option but to select a special process technology that trails the most current standard logic process by two or three technology generations. This choice generally requires additional processing steps that increase wafer costs. Alternatively, the team could implement a less efficient, more costly, slower, and larger two-chip solution by separating the SoC and the NVM into discrete components.
FIG. 1 illustrates a prior technique of creating a non-volatile memory cell. The previous technique created a two polysilicon layers for the nonvolatile memory cell. The second polysilicon layer was the word line, and the word line receives a bias voltage. The bias voltage is coupled from the word line to the first polysilicon layer, referred to as a floating gate, by a coupling capacitor. The floating gate is separated from the PWell of the polysilicon by an insulating material. The floating gate in connection with the PWell creates the cell channel or read transistor. The read transistor typically communicates the logical information stored by that particular memory cell during normal operations.
Typically, the read transistor for that memory cell functions as both the sensing component to communicate the information stored during normal operations, and a charging component to allow either erasing or programming information stored in that memory cell. The second polysilicon layer, the word line, typically is used to couple voltage into the floating poly gate either for write or read operations. Next, electrons charge through the coupling capacitor into the floating gate to store the information.
To create a prior non-volatile memory cell, typically a standard CMOS-based logic process is used as a starting foundation. Next, additional process steps are incorporated into the logic process flow to create the non-volatile memory cells. Examples of such additional process steps include second polysilicon deposition junction dopant optimization, etc. Integrating “non-volatile memory”-specific process steps into the standard CMOS-based logic process creates complications which require extensive qualifications. Consequently, embedded non-volatile memory technologies generally lag advanced logic fabrication processes by several generations. For a system-on-chip (SoC) approach, which requires embedding a non-volatile memory, a design team may have no choice but to accept a logic flow process usually two to three generations behind the current advanced standard logic process as well as the addition to that process of seven to eight additional lithographic masks. This prior approach not only typically increases the wafer cost, but also falls short of the peak performance that the most advanced standard logic process can deliver.
Also, the performance and reliability of a SiO2-based non-volatile memory cell typically degrades under extended program and erases operations due to the cycling-induced degradation of the SiO2. The previous technique of subjecting all of the non-volatile memory cell components to the higher program and erase voltages typically hastens the degradation of the SiO2.